Project Name: L2_Max_throughput

This Project tests the peak L2 throughput for write accesses with DMA masters from 
different SCBs accessing the L2 memory to write the Data. Data is transfered form L1 
memory to L2 memory, and a dat blobk size of 16K bytes us used. The default clock 
settings from XML are used i.e. 
	CCLK 	= 500 MHz
	SYSCLK 	=250 MHz
	SOCLK 	= 125 MHz
	SCLK1 	= 125 MHz
	SCLK 	= 250 MHz
	
 Following DMA channels are used to do the write accesses to L2 memory:
 	-MDMA stream 0  (DMA 21 & 22)
  	-PPI0 DMA (DMA 29)
  	-PPI1 DMA (DMA 33)
  	-PPI2 DMA (DMA 31)
  	-Link Port DMA
 
  