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	This directory is associated with Rev 1 of the Application Note


    		ADSP-BF60x Blackfin Processors System Optimization Techniques (EE-362)  


	that can be found at http://www.analog.com/ee-notes


	Analog Devices, Inc.
	DSP Division
	Three Technology Way
	P.O. Box 9106
	Norwood, MA 02062

	Date Created:    Nov 12th, 2013


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Description of the EE-Note:

	This application note discusses various system bandwidth optimization techniques for ADSP-BF60x Blackfin Processors.


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Bandwidth_Limit_Core0: 

	This code illustrates the bandwidth limit feature. It configures an MDMA from DMC and measures the throughput
	by polling the DMA status bit.


Bandwidth_Monitor_Core0: 

	This code illustrates the bandwidth monitor functionality. It configures a single MDMA channel 21-22 to read 
	from DMC.The bandwidth monitor register is programmed to monitor a minimum bandwidth of 400 MB/s. If the throughput is 
	less than 400 MB/s, the bandwidth monitor shall expire and and error message will be printed. Else, the bandwidth register
	 can be used to monitor the measured throughput instead of using the cycle count registers.


DMC_SCB_PRIO_Test_Core0: 

	This code runs two MDMA channels is parallel to read from the DMC. The DMC_PRIOx and DMC_PRIOMSKx 
	registers (ddr_test.c)* are programmed to elevate the priority of a particular MDMA channel to increase the DMC throughput 
	for that channel.


L2_Max_Throughput: 

	This Project tests the peak L2 throughput for write accesses with DMA masters from 
	different SCBs accessing the L2 memory to write the Data. Data is transfered form L1 
	memory to L2 memory, and a dat blobk size of 16K bytes us used. The default clock 
	settings from XML are used i.e. 
		CCLK 	= 500 MHz
		SYSCLK 	=250 MHz
		SOCLK 	= 125 MHz
		SCLK1 	= 125 MHz
		SCLK 	= 250 MHz
	
	Following DMA channels are used to do the write accesses to L2 memory:
 		-MDMA stream 0  (DMA 21 & 22)
	  	-PPI0 DMA (DMA 29)
  		-PPI1 DMA (DMA 33)
	  	-PPI2 DMA (DMA 31)
	  	-Link Port DMA


MDMA_Throughput_Measurements_Core0: 

	This code can be used to perform read and write throughput measurements for MDMA
	under various conditions: sequential, non-sequential, different MSIZE values,different DDR settings etc.


SCB_Optimization_Core0: 

	This project contains example code that shows how to program the SCB slots.


Stress_Test_Core0: 

	The example code involves the following conditions.

	CCLK=500 MHz, DCLK=250 MHz, SYSCLK = 250 MHz, SCLK0 = SCLK1=125 MHz
	SCB5
		o	PPI0 running in 24 bit transmit, internal clock and frame sync mode at PPICLK=62.5 MHz. 
			This requires a throughput = 62.5*3 = 187.5 MB/s.
		o	PPI2 running in 16 bit transmit, internal clock and frame sync mode at PPICLK=62.5 MHz. 
			This requires a throughput = 62.5*2 = 125 MB/s.
		o	The total throughput requirement by SCB5 from SCB0(MI0) = 187.5 + 125 = 312.5 MB/s
	SCB6
		o	PPI1 running in 16 bit transmit, and internal clock and frame sync mode at PPICLK=62.5 MHz.
		o	The total throughput requirement by SCB6 from SCB0(MI0) = 52.5*2 = 125 MB/s.
	SCB3
		o	Link Port 1 (LP1) and Link Port 0 (LP0) running in loopback with LP1 as transmitter and 
			LP0 as receiver with LPCLK = 62.5 MHz.
		o	The total throughput requirement by SCB6 from SCB0(MI0) = 62.5 MB/s
	SCB4
		o	MDMA0 channels (21-22) and MDMA1 channels (25-26).
		o	The throughput requirements for these channels depend upon the corresponding DMAx_BWLCNT register values.
			If they are not programmed, the MDMA channels request for the bandwidth with full throttle (every SCLK 
			cycle). This means that both the MDMA channels request to SCB4 for an individual throughput of 125*4 = 500 MB/s.
		o	However, since SCB4 runs on SCLK itself, the maximum total theoretical bandwidth request by SCB4 from 
			SCB0-MI0 is limited to 125*4 = 500 MB/s.
	
	The code can be run under different conditions by commenting/uncommenting the corresponding conditions/optimization techniques
	in the "Stress_Test_Core01.h" file.

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All code examples have been written and tested with:

	ADSP-BF609 silicon revision 0.1

	ADSP-BF609 EZ-KIT Lite board revision 1.0
        
        CrossCore Embedded Studio Tools version 1.0.2.0


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