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This ZIP File is associated with the Application Note


Tips and Tricks Using the ADSP-SC58x/2158x Processor Boot ROM (EE-384)

that can be found at http://www.analog.com/ee-notes.

Date Created:	09/30/2015

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CONTENTS

	1. DESCRIPTION
	2. VERSION INFORMATION
	3. DIRECTORY STRUCTURE
	4. EXTERNAL CONNECTIONS

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1. DESCRIPTION

This directory contains an example ADSP-SC58x project that shows how to generate boot streams for all three cores. It uses a simple LED blink example, which can be run on the ADSP-SC589 EZ-KIT Lite evaluation board and then verified with loader streams generated for SPI master boot mode.

It also includes the following:

a. Second-Stage Loader implementation making use of the adi_rom_Boot() API.

b. Sample code making use of the BITM_ROM_BFLAG_HOOK and BITM_ROM_BFLAG_RETURN flags supported by the ROM code.

c. Sample code making use of the OTP API to program/read the general-purpose space in the OTP.

The examples include generation of both secure and non-secure (standard) loader streams. For more information, refer to the readme.txt file inside each sub-directory.

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2. VERSION INFORMATION

Tested on:

IDE: CrossCore Embedded Studio 2.0.0
Hardware: ADSP-SC589 EZ-KIT Lite Revision 1.1
	BOM Revision 1.5
	Silicon Revision 0.1

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3. DIRECTORY STRUCTURE

- 1. Led_Blink_Code: each of the three cores toggles a single LED
	- Multicore_Led_Blink_Core0: Cortex-A5 Core0 toggles LED10.
	- Multicore_Led_Blink_Core1: SHARC+ Core1 toggles LED11.
	- Multicore_Led_Blink_Core0: SHARC+ Core2 toggles LED12.

- 2. Loader Streams: loader/boot streams generated for secure and non-secure (standard) boot
	- Keys: holds the keys used for encryption and authentication
	- LS1\Fill_block\HPC
		- Normal: Normal (standard) boot stream for SPI master, SPI slave, UART and LP
		- Secure_BLp: Secure boot stream for integrity/authenticity protection for SPI master, SPI slave, UART and LP
		- Secure_BLx: Secure boot stream for integrity/authenticity and confidentiality protection for SPI master, SPI slave, UART and LP
		- Secure_BLw: Secure boot stream for integrity/authenticity and confidentiality protection with wrapped encryption key for SPI master, SPI slave, UART and LP    

- 3. SSL_Code_Example: Second-Stage Loader on Cortex-A5 core
	- Multicore_Led_Blink_Core0: Secondary application that gets invoked from primary application and blinks LED10
	- SSL_Core0: Primary application that invokes ROM API to boot secondary application
	
- 4. ROM_API_Flags: example using ROM Hook function
	- Hook_Function_Core0: Shows use of 'BITM_ROM_BFLAG_HOOK' flag to boot an application runs on Cortex-A5 core0
	- Return_Flag_Core0: Shows use of 'BITM_ROM_BFLAG_RETURN' flag to boot SHARC+ application from Cortex-A5 core0
	
- 5. OTP API code: example of OTP programming
	- OTP_GP_Space_Programmming_Core0: Cortex-A5 programs/reads the GP space in the OTP

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4. EXTERNAL CONNECTIONS

- For SPI master boot mode, no external connections are required. The BMODE pin (SW1) must be in the 1 position.
- For SPI, UART, and LP slave boot modes, a host needs to be connected properly to the ADSP-SC589 processor, and the BMODE pin (SW1) must be in the 2, 6 or 7 positions for SPI slave, LP slave, and UART slave boot modes, respectively.
