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	This directory is associated with Rev 2 of the Application Note


    		Interfacing DDR3/DDR2/LPDDR memory devices with ADSP-SC5xx/ADSP-215xx processors  (EE-387)  


	that can be found at http://www.analog.com/ee-notes


	Analog Devices, Inc.
	DSP Division
	Three Technology Way
	P.O. Box 9106
	Norwood, MA 02062

	Date Created:    December 17th, 2015


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Description of the EE-Note:

	This application note discusses hardware and software guidelines for interfacing DDR3/DDR2/LPDDR devices with ADSP-SC5xx/ADSP-215xx processors.


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Custom Init Codes: 

	These codes provide examples for customized init codes for ADSP-SC589 and ADSP-SC584 processors. 


Custom Preload Codes: 

	These codes provide examples for customized preload codes for ADSP-SC589 and ADSP-SC584 processors. 

DDR2_Init_Core0 and DDR2_Init_Core1: 

	These codes can be run on ADSP-SC584 EZ-Kit to configure the Micron DDR2 device MT47H128M16RT-25E XIT:C.


DDR3_Init_Core0 and DDR3_Init_Core1: 

	These codes can be run on ADSP-SC589 EZ-Kit to configure the Micron DDR3 device MT41K128M16-125.


LPDDR_Init_Core0 and LPDDR_Init_Core1: 

	These codes can be run on ADSP-SC589 LPDDR board (ADI internal)to configure the Micron LPDDR device MT46H128M16LFDD-48 WT .


DDR2_Init_Two_CGU_Core0 and DDR2_Init_Two_CGU_Core1: 

	These codes can be run on ADSP-SC584 EZ-Kit to configure the Micron DDR2 device MT47H128M16RT-25E XIT:C with DCLK=400 MHz and CCLK=450 MHz using two CGUs.

DDR3_Re_Initialization_ARM_Core0: 

	This codes shows how to re-configure the DMC on ARM core when the ARM code is placed in DMC.
	
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All code examples have been written and tested with:

	ADSP-SC589 silicon revision 0.1

        CrossCore Embedded Studio Tools version 2.0.0


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