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This folder is associated with the Application Note


   	ADSP-CM40x Serial Flash Execute-in-Place Technology(EE-363)

that can be found at http://www.analog.com/ee-notes.

Date Created:	21/10/2015

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CONTENTS

	1. DESCRIPTION
	2. VERSION INFORMATION
	3. DIRECTORY STRUCTURE
	4. EXTERNAL CONNECTIONS

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1. DESCRIPTION

The folder contains the Memory_placement project that demostrates the placement of code on various memory regions and analyze performance of execution. This example is an add-on on top of the LED_Blink_Flash project with regards to execution speed analysis. The Linker COnfiguration File includes support for required memory regions.

Following memory regions are used:

1. Internal SRAM
2. Internal SPI Flash
3. External Async SRAM connected to SMC.
4. External Async SRAM connected to SMC, accessed via MEM-Y for cache.

Example Code Description :-

1. 	The code can demonstrate the execution speed with respect to LED blink or analysing performance against linear execution of 32-bit instructions.

	If RUN_PERF_ANALYSIS is not commented, then LinearCode() function will be called that executes 3996 bytes of ARM Cortex M4 instructions and RETURN instruction. Number of cycles taken that are printed out to the terminal IO window reflects the performance directly.

	If RUN_PERF_ANALYSIS is commented, then CallSomeFlashCode() function will be called that blinks LED. User can perceive the rate of blinking of LEDs against the placement into various memories.
	

2. 	Functions  LinearCode() and CallSomeFlashCode() will be placed in various types of memories as requested by user via following MACROS present in Memory_placement.h. If all the below MACROs are commented, then code will be placed to Internal SRAM.

	#define PLACE_FLASH          -- if defined, places function into SPI2 flash
	#define PLACE_ASYNCSRAM      -- if defined, places function into Async SRAM, 
	#define PLACE_MEMYCODE       -- if defined, places function into Async SRAM, 
					but using cache


3.	#define BYPASS_CACHE         -- if defined, bypasses cache 
	#define SET_CLOCKS	     -- for optimizing CGU and SPI clock
	#define PREFETCH ENABLE      -- to enable prefetch in the cache	
        #define XIP_ENABLE           -- to enable SPI Flash in XIP mode   


4.      Configure CCLK/SCLK in Project options> C/C++ Compiler> Preprocessor> Defined Symbols
	
	CCLK240_SCLK96	     -- configures CCLK/SCLK = 240Mhz/96Mhz	
	CCLK225_SCLK100      -- configures CCLK/SCLK = 225Mhz/100Mhz
	CCLK240_SCLK80       -- configures CCLK/SCLK = 240Mhz/80Mhz
	CCLK200_SCLK100	     -- configures CCLK/SCLK = 200Mhz/100Mhz

A local copy of the modified startup.c file including below modifications is avaible in Project Directory, which configures SMC pins.

	//configure SMC pins
	ProgramAsyncBus(); 

	//call IAR system startup
	__iar_init_core();
	__iar_init_vfp();
	__cmain();



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2. VERSION INFORMATION

Tested on:

IDE: 	  IAR Embedded Workbench for ARM 7.40.1
Hardware: ADSP-CM408F EZ-KIT board revision 0.2, BOM Revision 0.7
    	  ADSP-CM403F EZ-Kit board revision 1.0, BOM Revision 0.7
	  Silicon Revision H

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3. DIRECTORY STRUCTURE
		
- Memory_placement

	Init_CGU.c - Initializes CGU.
	Memory_placement.c - Contains main() function and places led blink code in configured memory location.
	Memory_placement.h - Contains User configurable MACROs. 
	PerfAnalysis.c - Consists of performance analysis function of a linear code.
	SystemUtil.c - Configures XIP mode, cache, clocks and different memory regions.
	startup.c - startup.c modified to add ProgramAsyncBus() function which configures SMC pins.
	system.c 


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4. EXTERNAL CONNECTIONS

None
